1. Field of the Invention
The present invention relates to a parallel type analog-to-digital conversion circuit, and a sampling circuit and a comparison amplification circuit each of which is used in the same.
2. Description of Related Art
Heretofore, there has been known a sampling circuit for canceling an offset voltage of an amplifier, amplifying an input signal and outputting the input signal thus amplified. FIG. 19A is a circuit diagram showing a configuration of this sampling circuit, and FIG. 19B is a timing chart explaining an internal operation of the sampling circuit.
A configuration of a sampling circuit 100 shown in FIG. 19A is described as follows. That is to say, an input signal Vin is inputted to an input side of an amplifier A100 through a switch SW100, and the input side of the amplifier A100 is adapted to be connected to the grounding potential (the ground in this case) through a switch SW101. Also, one terminal of a capacitor C100 is connected to an output terminal of the amplifier A100, and a switch SW102 is provided between the other terminal of the capacitor C100, and the grounding potential (ground).
The sampling circuit 100 operates in two phases of a reset phase and a signal output phase, and cancels an offset voltage of the amplifier A100 and amplifies the input signal Vin to the amplifier A100. That is to say, as shown in FIG. 19B, in the reset phase (for a time period from t1 to t2 and from t3 to t4), each of the switches SW101 and SW102 is held in an ON state to provide a state in which no input voltage Vin is inputted to the amplifier A100. In this case, the capacitor C100 is charged with the electric charges based on the offset voltage of the amplifier A100, and thus the offset voltage of the amplifier A100 is sampled by the capacitor C100. After that, in the signal output phase (for a time period from t2 to t3 and from t4 to t5), each of the switches SW101 and SW102 is held in an OFF state, and the switch SW100 is held in the ON state. In this case, the input signal Vin is inputted to the amplifier A100, an output signal Vo1 obtained by amplifying the input signal Vin in the amplifier A100 is outputted from the amplifier A100. Also, an output signal Vo2 obtained by subtracting the offset voltage of the amplifier A100 from the output signal Vo1 is outputted through the capacitor C100.
Here, a comparison amplification circuit with a track & hold (T/H) function is known as one of the circuits each of which is configured by using the principles of the sampling circuit 100. FIG. 20A is a circuit diagram showing a configuration of a comparison amplification circuit in the related art.
A configuration of the comparison amplification circuit 110 is described as follows. That is to say, as shown in FIG. 20A, an input signal Vin and a reference signal Vr are inputted to an amplifier A110 through switches SW110 and SW111, and a capacitor C110, and an input side of the amplifier A110 is adapted to be connected to the grounding potential (the ground in this case) through a switch SW112. On the other hand, one terminal of a capacitor C111 is connected to an output terminal of the amplifier A110, and a switch SW113 is provided between the other terminal of the capacitor C111 and the grounding potential (ground).
Also, as shown in FIG. 20B, the comparison amplification circuit 110 operates in two phases of a reset phase and a signal output phase.
In the reset phase, each of the switches SW110, SW112 and SW113 is held in an ON state, and the switch SW111 is held in an OFF state. At this time, the capacitor C110 as a capacitor for comparison is charged with the electric charges based on the input signal Vin, and thus the voltage of the input signal Vin is sampled by the capacitor C110. Moreover, a state is provided in which no input signal Vin is inputted to the amplifier A110. As a result, the capacitor C111 is charged with the electric charges based on the offset voltage of the amplifier A110, and thus the offset voltage is sampled by the capacitor C111.
In the signal output phase, each of the switches SW110, SW112 and SW113 is held in an OFF state, and the switch SW111 is held in an ON state. For this reason, an output signal Vo1 obtained by amplifying a voltage difference between the input signal Vin and the reference signal Vr in the amplifier A110 is outputted from the amplifier A110. Also, an output signal Vo2 obtained by subtracting the offset voltage of the amplifier A110 from the output signal Vo1 is outputted through the capacitor C111.
Such a comparison amplification circuit 110, for example, is used in a parallel type analog-to-digital conversion circuit 120 or the like. FIG. 21 is a circuit diagram showing a configuration of the parallel type analog-to-digital conversion circuit 120 in the related art.
Now, as shown in FIG. 21, the parallel type analog-to-digital conversion circuit 120 is generally configured by using comparison amplification circuits only for the resolution (for example, in the case of an n-bit analog-to-digital conversion circuit, (2n−1) comparison amplification circuits). However, recently, a parallel type analog-to-digital conversion circuit using a resistive interpolation technique or a capacitive interpolation technique (hereinafter referred to as “an interpolation parallel type analog-to-digital conversion circuit) has attracted attention. This interpolation parallel type analog-to-digital conversion circuit, for example, is described in Japanese Patent Laid-Open No. 2003-100774.
Here, FIG. 22 shows a configuration of the interpolation parallel type analog-to-digital conversion circuit using the capacitive interpolation technique. A comparison amplification portion 132 using the capacitive interpolation technique is configured in the interpolation parallel type analog-to-digital conversion circuit shown in FIG. 22. It is noted that only a part of the comparison amplification portion 132 is illustrated herein for the sake of facilitating the understanding thereof.
The comparison amplification portion 132 generates voltage differences Vs1 and Vs2 between reference signals Vra and Vrb generated in a reference signal generating portion 131, and an input signal Vin in voltage difference generating portions 133a and 133b, respectively.
In a first amplifier group 134, the voltage differences Vs1 and Vs2 are amplified in a plurality of amplifiers A130a and A130b, respectively, and an intermediate voltage between the voltage differences Vs1 and Vs2 is amplified in an amplifier A130c. 
A second amplifier group 135 includes a plurality of amplifiers A131a to A131c for amplifying voltages from the amplifiers A130a to A130c in the first amplifier group 134. In addition thereto, the second amplifier group 135 includes a plurality of amplifiers A131d and A131e for amplifying an intermediate voltage between output voltages from the amplifiers A130a and A130c, and an intermediate voltage between output voltages from the amplifiers A130b and A130c, respectively.
Each of output signals from the amplifiers A131a to A131e is outputted through one capacitors Ca and two capacitors Cb. Each of the output signals from the amplifiers A131a to A131e is outputted after each of the offset voltages of the amplifiers A131a to A131e is canceled through the capacitor Ca. In addition, the adjacent amplifiers (for example, the amplifiers A131a and A131d, and the amplifiers A131d and A131b) are each connected to each other through the two capacitors Cb. Thus, the output signals from the adjacent amplifiers are outputted after the offset voltages thereof are canceled and composed with each other. At this time, the capacitance value of the capacitor Cb is made half that of the capacitor Ca, which results in that the intermediate voltage between the output voltages from the amplifiers A131a and A131c, the intermediate voltage between the output voltages from the amplifiers A131b and A131e, and the intermediate voltage between the output voltages from the amplifiers A131e and A131c are each outputted through the capacitors Cb, respectively.
The output voltages through the capacitors Ca and Cb are successively latched in latch circuits in a latch portion in a subsequent stage. Also, encoding based on latch states in the latch circuits is carried out in an encoder, thereby obtaining a digital signal.
The number of amplifiers in the comparison amplification portion can be reduced in the interpolation parallel type analog-to-digital conversion circuit because of adoption of such a circuit configuration.